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stm32 /stm32wl3 /STM32WL33 /TIM2 /AF1

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Interpret as AF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ETR_SEL 0 (ETR_SEL_3)ETR_SEL_3

Description

AF1 register

Fields

ETR_SEL

ETRSEL[2:0]: External trigger source selection

000: TIMx External trigger legacy mode

001: TIMx External trigger source select COMP1_OUT

Other: Reserved

Note: These bits can’t be modified as long as LOCK level 1 has been programmed (LOCK

bits in TIMx_BDTR register)
ETR_SEL_3

ETRSEL[2:0]: External trigger source selection

This field is not used in Blue51. Not available in IUM

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32