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stm32 /stm32wl3 /STM32WL33 /TIM2 /OR1

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Interpret as OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ETR_RMP)ETR_RMP 0 (OR1_1)OR1_1 0 (TI4_RMP)TI4_RMP

Description

OR1 register

Fields

ETR_RMP

ETR_RMP: ETR remapping capability

0: TIMx_ETR is not connected to ADC AWD (must be selected when the ETR comes from

the ETR input pin)

1: TIMx_ETR is connected to ADC AWD

Note: ADC AWD source is ‘ORed’ with the TIMx_ETR input signals. When ADC AWD is used,

it is necessary to make sure that the corresponding TIMx_ETR input pin is not enabled

in the alternate function controller.
OR1_1

This field is not used in Blue51. Not available in IUM
TI4_RMP

TI4_RMP: Input capture 4 remap

0: TIM2 input capture 4 is connected to I/O

1: TIM2 input capture 4 is connected to COMP1-OUT

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32