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stm32 /stm32wl3 /STM32WL33 /TIM2 /TISEL

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Interpret as TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL0TI2SEL0TI3SEL0TI4SEL

Description

TISEL register

Fields

TI1SEL

TI1SEL[3:0]: selects TI1[0] to TI1[15] input

0000: TIMx_CH1 input

Others: Reserved
TI2SEL

TI2SEL[3:0]: selects TI2[0] to TI2[15] input

0000: TIMx_CH2 input

Others: Reserved
TI3SEL

TI3SEL[3:0]: selects TI3[0] to TI3[15] input

0000: TIMx_CH3 input

Others: Reserved
TI4SEL

TI4SEL[3:0]: selects TI4[0] to TI4[15] input

0000: TIMx_CH4 input

Others: Reserved

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32